HD64F3694HV Datasheet, PDF (332/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 20 List of Registers
20.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Register Name
Abbre- Bit
Module
viation No Address Name
—
—
—
Low-voltage detection control
register
LVDCR 8
Low-voltage detection status register LVDSR 8
H'F000 to —
H'F72F
H'F730 LVDC*¹
H'F731 LVDC*¹
—
—
— H'F732 to —
H'F747
I²C bus control register 1
ICCR1 8 H'F748 IIC2
I²C bus control register 2
ICCR2 8 H'F749 IIC2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
ICMR 8 H'F74A IIC2
ICIER 8 H'F74B IIC2
ICSR 8 H'F74C IIC2
Slave address register
I²C bus transmit data register
I²C bus receive data register
SAR
8
ICDRT 8
ICDRR 8
H'F74D IIC2
H'F74E IIC2
H'F74F IIC2
—
—
— H'F750 to —
H'FF7F
Timer mode register W
TMRW 8 H'FF80 Timer W
Timer control register W
TCRW 8 H'FF81 Timer W
Timer interrupt enable register W TIERW 8 H'FF82 Timer W
Timer status register W
TSRW 8 H'FF83 Timer W
Timer I/O control register 0
TIOR0 8 H'FF84 Timer W
Timer I/O control register 1
TIOR1 8 H'FF85 Timer W
Timer counter
TCNT 16 H'FF86 Timer W
General register A
GRA
16 H'FF88 Timer W
Data
Bus
Width
—
Access
State
—
8
2
8
2
—
—
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
—
—
8
2
8
2
8
2
8
2
8
2
8
2
16*²
2
16*²
2
Rev.5.00 Nov. 02, 2005 Page 302 of 418
REJ09B0028-0500