HD64F3694HV Datasheet, PDF (24/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3)
Figure 14.1 Block Diagram of SCI3........................................................................................... 190
Figure 14.2 Data Format in Asynchronous Communication ...................................................... 205
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 205
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 206
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 207
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 208
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 209
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 211
Figure 14.8 Sample Serial Reception Data Flowchart (2) .......................................................... 212
Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 213
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 215
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 216
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 217
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 218
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit
and Receive Operations (Clocked Synchronous Mode) ........................................ 220
Figure 14.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 222
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 223
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 225
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 226
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 227
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 230
Section 15 I²C Bus Interface 2 (IIC2)
Figure 15.1 Block Diagram of I²C Bus Interface 2..................................................................... 232
Figure 15.2 External Circuit Connections of I/O Pins ................................................................ 233
Figure 15.3 I²C Bus Formats ...................................................................................................... 246
Figure 15.4 I²C Bus Timing........................................................................................................ 246
Figure 15.5 Master Transmit Mode Operation Timing (1)......................................................... 248
Figure 15.6 Master Transmit Mode Operation Timing (2)......................................................... 248
Figure 15.7 Master Receive Mode Operation Timing (1) .......................................................... 250
Figure 15.8 Master Receive Mode Operation Timing (2) .......................................................... 251
Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 252
Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 253
Rev.5.00 Nov. 02, 2005 Page xxii of xxviii