HD64F3694HV Datasheet, PDF (258/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3)
14.7 Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6
shows the interrupt sources.
Table 14.6 SCI3 Interrupt Requests
Interrupt Requests
Receive Data Full
Transmit Data Empty
Transmission End
Receive Error
Abbreviation
RXI
TXI
TEI
ERI
Interrupt Sources
Setting RDRF in SSR
Setting TDRE in SSR
Setting TEND in SSR
Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the
generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
Rev.5.00 Nov. 02, 2005 Page 228 of 418
REJ09B0028-0500