HD64F3694HV Datasheet, PDF (239/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3)
14.4.4 Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Serial
data
Start
bit
Receive
data
Parity Stop Start
bit bit bit
Receive
data
Parity Stop Mark state
bit bit (idle state)
1 0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
1
1 frame
1 frame
RDRF
FER
LSI
operation
User
processing
RXI request RDRF
cleared to 0
RDR data read
0 stop bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev.5.00 Nov. 02, 2005 Page 209 of 418
REJ09B0028-0500