HD64F3694HV Datasheet, PDF (81/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 3 Exception Handling
3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)
• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt flag register 1 (IRR1)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.
Initial
Bit
Bit Name Value
7
NMIEG 0
6 to 4 
All 1
3
IEG3
0
2
IEG2
0
1
IEG1
0
0
IEG0
0
R/W
R/W

R/W
R/W
R/W
R/W
Description
NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
Reserved
These bits are always read as 1.
IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
IRQ2 Edge Select
0: Falling edge of IRQ2 pin input is detected
1: Rising edge of IRQ2 pin input is detected
IRQ1 Edge Select
0: Falling edge of IRQ1 pin input is detected
1: Rising edge of IRQ1 pin input is detected
IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
Rev.5.00 Nov. 02, 2005 Page 51 of 418
REJ09B0028-0500