HD64F3694HV Datasheet, PDF (280/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 15 I²C Bus Interface 2 (IIC2)
Master transmit mode
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
A
TDRE
Master receive mode
1
2
3
4
5
6
7
8
9
1
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
Data 1
User
processing
[1] Clear TDRE after clearing [2] Read ICDRR (dummy read)
TEND and TRS
[3] Read ICDRR
Figure 15.7 Master Receive Mode Operation Timing (1)
Rev.5.00 Nov. 02, 2005 Page 250 of 418
REJ09B0028-0500