HD64F3694HV Datasheet, PDF (205/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 12.16 shows the output compare timing.
Section 12 Timer W
φ
TCNT input
clock
TCNT
N
N+1
GRA to GRD
N
Compare
match signal
FTIOA to FTIOD
Figure 12.16 Output Compare Output Timing
12.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
φ
Input capture
input
Input capture
signal
TCNT
N–1
N
N+1
N+2
GRA to GRD
N
Figure 12.17 Input Capture Input Signal Timing
Rev.5.00 Nov. 02, 2005 Page 175 of 418
REJ09B0028-0500