HD64F3694HV Datasheet, PDF (227/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3)
Initial
Bit
Bit Name Value R/W Description
3
PER
0
R/W Parity Error
[Setting condition]
• When a parity error is generated during reception
[Clearing condition]
• When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End
[Setting conditions]
• When the TE bit in SCR3 is 0
• When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
[Clearing conditions]
• When 0 is written to TEND after reading TEND = 1
• When the transmit data is written to TDR
1
MPBR
0
R
Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is cleared to 0,
its previous state is retained.
0
MPBT
0
R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
Rev.5.00 Nov. 02, 2005 Page 197 of 418
REJ09B0028-0500