HD64F3694HV Datasheet, PDF (228/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3)
14.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (high-
speed) mode. Table 14.4 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 in SMR in clocked synchronous mode. The values shown in table 14.4 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
φ
64 × 2^2n–1 × B
× 10⁶ – 1
Error
(%)
=

_(N
+
1)
φ
×
×
B
10⁶
× 64
×
2^2n–1
–1
× 100
[Clocked Synchronous Mode]
N=
φ
8 × 2^2n–1 × B
× 10⁶ – 1
Note: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CKS1 and CKS0 setting for SMR (0 ≤ N ≤ 3)
Rev.5.00 Nov. 02, 2005 Page 198 of 418
REJ09B0028-0500