HD64F3694HV Datasheet, PDF (278/452 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 15 I²C Bus Interface 2 (IIC2)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W
A
1
2
Bit 7 Bit 6
TEND
ICDRT
Address + R/W
Data 1 Data 2
ICDRS
Address + R/W
Data 1
User
[2] Instruction of start
processing
condition issuance
[3] Write data to ICDRT (first byte)
[4] Write data to ICDRT (second byte)
[5] Write data to ICDRT (third byte)
Figure 15.5 Master Transmit Mode Operation Timing (1)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
TEND
ICDRT
ICDRS
9
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
A/A
Data n
Data n
User _{[5] Write data to ICDRT}
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 15.6 Master Transmit Mode Operation Timing (2)
Rev.5.00 Nov. 02, 2005 Page 248 of 418
REJ09B0028-0500