HD66789 Datasheet, PDF (90/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
The timing chart of 6-bit RGB interface is as follows.
Preliminary
Back porch period
VSYNC
HSYNC
DOTCLK
ENABLE
VLD
PD17-0
1 frame
Front porch period
>= 1H
VSYNC
HLW>=3CLK
HSYNC
DOTCLK
1 clock
ENABLE
VLD
DTST >= HLW
PD17-0
1H
RGB RGB RGB
RGB RGB
Valid data
VLW: the period in which VSYNC is low level
HLW: the period in which HSYNC is low level
DTST: the set up time for data transmission
Note 1) In 6-bit interface.mode, one pixel, which consists of R,G, and B, must be transmitted in synchronization
with 3 DOTCLKs.
Note 2) VSYNC, HSYNC, EVABLE, DOTCLK, VLD, and PD17-2 should be all transmitted by three clocks.
Note 3) Data to be displayed must be written in the high-speed write mode (HWM =1) in RGB I/F mode.
6-bit RGB Interface Timing
Rev.0.12, May 09 2003, page 90 of 156