HD66789 Datasheet, PDF (145/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
Clock Synchronized Serial Interface Timing Characteristics
Vcc = 1.8 to 2.4 V
Item
Symbol Unit Test Condition Min
Write
(received)
t_SCYC
us
Figure 3
0.1
Serial clock cycle time
Read
(transmitted t_SCYC us
Figure 3
0.5
)
Serial clock high-level pulse
width
Serial clock low-level pulse
width
Write
(received)
t_SCH
ns
Figure 3
40
Read
T.B.D. ^{(transmitted tSCH ns}
Figure 3
230
)
Write
(received)
t_SCL
ns
Figure 3
40
Read
(transmitted t_SCL ns
Figure 3
230
)
Serial clock rise/fall time
t_{scr, tscf} ns
Figure 3
—
Chip select set up time
t_CSU ns
Figure 3
20
Chip select hold time
t_CH ns
Figure 3
60
Serial input data set up time
t_SISU ns
Figure 3
30
Serial input data hold time
t_SIH
ns
Figure 3
30
Serial input data delay time
t_SOD ns
Figure 3
—
Serial input data hold time
t_SOH ns
Figure 3
5
Typ Max
— 20
— 20
——
——
——
——
— 20
——
——
——
——
— 200
——
Vcc = 2.4 to 3.3 V
Item
Symbol Unit
Test
Condition
Serial clock cycle time
Write
t_SCYC us
(receive))
Read
(send)
t_SCYC us
Figure 3
Figure 3
Write
t_SCH
ns
Figure 3
Serial clock high-level pulse
(receive)
T.B.D. ^width
Serial clock low-level pulse
Read
(send)
t_SCH
ns
Write
t_SCL
ns
(receive)
Figure 3
Figure 3
width
Read
t_SCL
ns
Figure 3
(send)
Serial clock rise/fall time
t_{scr, scf} ns
Figure 3
Chip select set up time
t_CSU
ns
Figure 3
Chip select hold time
t_CH
ns
Figure 3
Serial input data set up time
t_SISU
ns
Figure 3
Serial input data hold time
t_SIH
ns
Figure 3
Serial output data delay time
t_SOD
ns
Figure 3
Serial output data hold time
t_SOH
ns
Figure 3
Min Typ Max
0.1 — 20
0.35 — 20
40 — —
150 — —
40 — —
150 — —
—
—
20
20 — —
60 — —
30 — —
30 — —
— — 130
5
—
—
Rev.0.12, May 09 2003, page 145 of 156