HD66789 Datasheet, PDF (142/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
AC Characteristics
(V_CC = 1.7 to 3.7 V, Ta = –40 to +85°C ^{Note 1})
Clock Characteristics (V_CC = 1.8 to 3.7 V)
Item
Symbol Unit Test Condition
Min
External clock
fcp
kHz VCC = 1.8 to 3.3 V
100
frequency
T.B.D. ^{External clock duty}
ratio
External clock rise time
Duty
trcp
%
VCC = 1.8 to 3.3 V
45
µs
VCC = 1.8 to 3.3 V
—
External clock fall time tfcp
µs
VCC = 1.8 to 3.3 V
—
R-C oscillation clock
fOSC
kHz Rf = TBD VCC = 3 V 244
Typ Max
270 600
50 55
— 0.2
— 0.2
305 366
Notes
9
9
9
9
10
80-system Bus Interface Timing Characteristics
Normal Write Mode (HWM=0) (Vcc = 1.8 to 2.4 V)
Item
Symbol Unit Test Condition Min Typ Max
Write
Bus cycle time
Read
t_CYCW
ns
t_CYCR
ns
Figure 2
Figure 2
600 — —
800 — —
Write low-level pulse width
PW_LW ns
Figure 2
90 — —
Read low-level pulse width
PW_LR
ns
Figure 2
350 — —
Write high-level pulse width
PW_HW ns
Figure 2
300 — —
Read high-level pulse width
PW_HR ns
Figure 2
400 — —
Write/Read rise/fall time
t_{WRr, WRf} ns
Figure 2
— — 25
T.B.D. Setup time Write (RS to CS*,WR*)
t_AS
Read (RS to CS*, RD*)
Address hold time
t_AH
ns
Figure 2
ns
Figure 2
0
10
5
—
—
—
—
—
—
VLD setup time
t_VS
ns
Figure 2
60 — —
VLD hold time
t_VH
ns
Figure 2
15 — —
Write data set up time
t_DSW
ns
Figure 2
60 — —
Write data hold time
t_H
ns
Figure 2
15 — —
Read data delay time
t_DDR
ns
Figure 2
— — 200
Read data hold time
t_DHR
ns
Figure 2
5
——
Rev.0.12, May 09 2003, page 142 of 156