HD66789 Datasheet, PDF (87/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
Internal Clock Operation to VSYNC Interface
VSYNC Interface to Internal Clock Operation
Internal clock operation
HWM = 1, AM = 0
Address Setting
VSYNC interface mode
setting (DM1-0 = 0, RM = 0)
Index register set (R22h)
Wait more than 1 frame
VSYNC interface
Write data to RAM
VSYNC interface
operation
VSYNC interface operation
Display operation
in synchronization with
the internal clock
The values set in DM1-0 and RM
become valid after completion of
1-frame display.
Internal clock mode setting
(DM1-0 = 0, RM = 0)
Wait more than 1 frame
Internal clock operation
Display operation
in synchronization with
VSYNC
The values set in DM1-0 and RM
become valid after completion of
1-frame display.
Display operation
in synchronization with
the internal clock
Note: When switching into the internal clock mode,the VSYNC signal
must be kept continuously supplied for more than 1 frame
after it is switched into the internal clock mode.
Displa y operation
in synchronization with
VSYNC
Internal clock mode setting
(DM1-0 =00, RM = 0)
Wait more than 1 frame
Internal clock operation
Note: When t he interface mode is switched, VSYNC should be
input before setting of DM1-0 and RM.
Transition flow between VSYNC and internal clock operation modes
Rev.0.12, May 09 2003, page 87 of 156