HD66789 Datasheet, PDF(34/156 Page) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD66789 Datasheet, PDF (34/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

◁

HD66789

Preliminary

HWM: When HWM=1, data are written to GRAM in high speed. In high-speed write mode, 4 words are

written to GRAM in a single operation after executing 4 RAM write operations. If RAM write is

terminated before it is executed 4 times, the last data will not be written. Make sure that RAM write is

executed 4 times. For this reason, the lower 2 bits must be set to â0â when setting the RAM address. For

details, see âHigh-Speed RAM Write Modeâ section.

I/D1-0: The address counter is automatically incremented by 1, after data are written to GRAM when I/D1-

0 = â1â. The address counter is automatically decremented by 1, after data are written to GRAM when

I/D1-0 = â0â. An independent setting for the increment or decrement of the address counter can be made to

the upper (AD15-8) and the lower (AD7-0) bits of the address. The address transition direction when data

are written to GRAM is set with AM bits.

AM: Set the direction of updating address counter automatically after data are written to GRAM. When

AM = â0â, the address counter is updated in the horizontal direction. When AM = â1â, the address counter

is updated in the vertical direction. When the window address is specified, data are written to the GRAM

area specified by the window address in the manner specified with I/D1-0, AM bits.

TRI DFM1 DFM0

0 00

10*

11 0

11 1

8-bit interface data format

First transmission

Second transmission

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

First transmission

Setting disabled

Second transmission

Third transmission

DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

First transmission

Second transmission

Third transmission

DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

8-bit interface data format

Rev.0.12, May 09 2003, page 34 of 156

▷