HD66789 Datasheet, PDF (43/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
SDT Bits
SDT1
SDT0
Delay Time for Source Signal
Internal Operation
(synchronized with the internal operating clock)
RGB I/F Operation
(synchronized with DOTCLK)
0
0
1 clock
8 clocks
0
1
2 clocks
16 clocks
1
0
3 clocks
24 clocks
1
1
4 clocks
32 clocks
Note 1) The amount of delay for the source output is measured from the falling edge of the CL1.
1H period
CL1
1H period
M
Gn
Sn
EQ
Source output delay
equalizing period
Source output delay and equalize period
Note 1) In internal operation and VSYNC interface modes, the reference clock is the internal operating clock.
In RGB interface modes, the reference clock is DOTCLK.
NO1-0: Specify the amount of non-overlap time for the gate output.
In the internal operation and VSYNC interface modes, the reference clock is the internal operating clock.
In the RGB interface mode, the reference clock is DOTCLK.
NO Bits
Non-overlap time
NO1
NO0
Internal Operation
(synchronized with the internal operating clock)
RGB I/F Operation
(synchronized with DOTCLK)
0
0
0 clock
0 clock
0
1
4 clocks
32 clocks
1
0
6 clocks
48 clocks
1
1
8 clocks
64 clocks
Note 1) The amount of non-overlap time is defined from the falling edge of the CL1.
Rev.0.12, May 09 2003, page 43 of 156