HD66789 Datasheet, PDF (46/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
Setting for external display interface control allows selecting an optimum interface for the kind of display
as follows. When displaying a moving picture (RGB-I/F/VSYNC-I/F), the display data must be written in
the high-speed mode (HWM = 1) which enables high-speed RAM access with low power consumption.
Display state and interfaces
Display State
Operation Mode RAM Access
(RM)
Display Operation Mode (DM1-0)
Still pictures
Internal clock
operation
System interface Internal clock operation
(RM = 0)
(DM1-0 = 00)
Moving pictures
RGB interface (1) RGB interface
(RM = 1)
RGB interface
(DM1-0 = 01)
Rewrite still picture
area while displaying
moving pictures.
RGB interface (2) System interface RGB interface
(RM = 0)
(DM1-0 = 01)
Moving pictures
VSYNC interface System interface VSYNC interface
(RM = 0)
(DM1-0 = 10)
Note 1)The instruction register setting is made only through a system interface.
Note 2) Switching between RGB-I/F and VSYNC-I/F cannot be made.
Note 3) The RGB-I/F mode settings is not changeable during RGB I/F operation.
Note 4) For details on the transition flow between operation modes, see the “External Display Interface”
section.
Note 5) Use the high-speed write mode (HWM = 1) during the write operation in RGB-I/F and VSYNC-I/F
modes.
Internal clock operation mode
All display operations are controlled by signals generated by the internal clock in internal clock operation
mode. All inputs through the external display interface are invalid. The internal RAM is accessible only
through a system interface.
RGB interface mode (1)
Display operation is controlled by the frame synchronization clock (VSYNC), line synchronizing signal
(VSYNC), and dot clock (DOTCLK) in the RGB interface mode. These signals must be supplied
throughout the display operation in this mode.
All display data are stored in the internal RAM, transmitted with PD17-0 bits by pixel. The combination
with the high-speed write mode and window address function enables simultaneous display of both moving
picture areas and the internal RAM area. The data are transmitted only when the screen is being updated,
thereby reducing the overall data transmission to minimum.
The periods of the front (FP) and back (BP) porches and the display period (NL) are automatically
generated in the HD66782 by counting the clock of line synchronizing signal (HSYNC) in accordance to
the frame synchronizing signal (VSYNC). Transmit pixel data with PD 17-0 bits in accordance with the
setting specified above.
Rev.0.12, May 09 2003, page 46 of 156