HD66789 Datasheet, PDF (89/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
VLD and ENABLE signals
The relationship with the VLD and ENABLE signals is as follows. With the ENABLE signal, the
addresses are not updated during data write, while with the VLD signal, the addresses are updated during
data write when the ENABLE is “Low”. The polarity of the ENABLE signal is inverted by the setting of
EPL bit.
EPL
ENABLE
VLD
0
0
0
0
0
1
0
1
*
1
0
*
1
1
0
1
1
1
RAM Write
Valid
Invalid
Invalid
Invalid
Valid
Invalid
RAM Address
Updated
Updated
Unchanged
Unchanged
Updated
Updated
RGB interface timing
The timing chart of 16/18-bit RGB interfaces is as follows.
Back porch period
VSYNC
HSYNC
DCOTCLK
ENABLE
VLD
PD17-0
1 frame
Front porch period
VSYNC
HLW >= 1CLK
HSYNC
DOTCLK
1 clock
ENABLE
VDL
DTST >=HLW
>=1H
1H
PD17-0
Valid data
VLW: the period in which VSYNC is low level
HLW: the period in which HSYNC is low level
DTST:the set up time for data transmission
Note: Data to be displayed must be written in the high-speed write mode (HWM = 1) in
RGB I/F mode.
16-/18-bit RGB Interface Timing
Rev.0.12, May 09 2003, page 89 of 156