HD66789 Datasheet, PDF (147/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
RGB interface timing characteristics
18/16 bit RGB interface (HWM =1), Vcc = 1.8V to 2.4V
Item
VSYNC/HSYNC Set up time
Symbol
tSYNCS
Unit
clock
Test
Condition
Figure 5
ENABLE Set up time
ENABLE Hold time
tENS
tENH
ns
Figure 5
ns
Figure 5
VLD Set up time
tVLS
ns
Figure 5
T.B.D. ^{VLD Hold time}
DOTCLK “Low” Level pulse
width
DOTCLK “High” Level pulse
width
tVLH
PWDL
PWDH
ns
Figure 5
ns
Figure 5
ns
Figure 5
DOTCLK cycle time
tCYCD
ns
Figure 5
Data Set up time
tPDS
ns
Figure 5
Data Hole time
tPDH
ns
DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5
Figure 5
Preliminary
min.
0
20
80
20
80
90
90
200
20
80

typ.
max.

1



















25
18/16 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.7 V
Item
VSYNC/HSYNC Set up time
Symbol
tSYNCS
Unit
clock
Test
Condition
Figure 5
min.
0
typ.
max.

1
ENABLE Set up time
tENS
ns
Figure 5
10


ENABLE Hold time
tENH
ns
Figure 5
20


VLD Set up time
tVLS
ns
Figure 5
10


T.B.D. ^{VLD Hold time}
DOTCLK “Low” Level pulse
width
tVLH
PWDL
ns
Figure 5
ns
Figure 5
40
40
DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
40






DOTCLK cycle time
tCYCD
ns
Figure 5
100


Data Set up time
tPDS
ns
Figure 5
10


Data Hole time
tPDH
ns
Figure 5
40


DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5


25
Rev.0.12, May 09 2003, page 147 of 156