HD66789 Datasheet, PDF (18/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
Block Function
1. System Interface
The HD66789 has five high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus and Serial Peripheral
Interface (SPI) port. The interface mode is selected with IM3-0 pins.
The HD66789 has three registers: 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit
read-data register (RDR). The IR stores index information from control registers and GRAM. The WDR
temporarily stores data to write into the control registers and GRAM, and the RDR temporarily stores data
read from GRAM. Data written into GRAM from the MPU is first written into the WDR and then
automatically written into GRAM by internal operation. Since data are read through the RDR from GRAM,
the data read out first are invalid data and the ensuing data are read out normally.
The execution time for instructions other than oscillation start is 0-clock cycle, which enables consecutively
writing instructions.
Register Selection (8/9/16/18 Parallel Interfaces)
80-system Bus
WR*
RD*
RS
Operation
0
1
0
Write index to IR
1
0
0
Read internal status
0
1
1
Write to the control registers or GRAM through WDR
1
0
1
Read from GRAM through RDR
Values of CS and VLD during RAM Write
CS*
VLD
Operations
0
0
Write data to GRAM. RAM address is updated.
1
0
Not write data to GRAM. RAM address is not updated.
0
1
Not write data to GRAM. RAM address is updated.
1
1
Not write data to GRAM. RAM address is not updated.
Note 1) The VLD setting is only effective with RAM write instructions.
Register Selection (Serial Peripheral Interface)
Start bytes
R/W
RS
0
0
1
0
0
1
1
1
Operations
Write index to IR
Read internal status
Write into control register and GRAM through WDR
Read from GRAM through RDR
Rev.0.12, May 09 2003, page 18 of 156