HD66789 Datasheet, PDF (53/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
VCM4 VCM3 VCM2 VCM1 VCM0 VcomH
0
0
0
0
0
VREG1OUT x 0.40
0
0
0
0
1
VREG1OUT x 0.42
0
0
0
1
0
VREG1OUT x 0.44
:
:
:
:
:
:
0
1
1
0
0
VREG1OUT x 0.64
0
1
1
0
1
VREG1OUT x 0.66
0
1
1
1
0
VREG1OUT x 0.68
0
1
1
1
1
Halt internal volume.
Adjust with a variable
external resistor from
VcomR.
1
0
0
0
0
VREG1OUT x 0.70
1
0
0
0
1
VREG1OUT x 0.72
1
0
0
1
0
VREG1OUT x 0.74
:
:
:
:
:
:
1
1
1
0
0
VREG1OUT x 0.94
1
1
1
0
1
VREG1OUT x 0.96
1
1
1
1
0
VREG1OUT x 0.98
1
1
1
1
1
Halt internal volume.
Adjust with a variable
external resistor from
VcomR.
VDV4 VDV3 VDV2 VDV1 VDV0 Vcom amplitude
0 0 0 0 0 VREG1OUT x 0.60
0 0 0 0 1 VREG1OUT x 0.63
0 0 0 1 0 VREG1OUT x 0.66
:
:
:
:
:
:
0 1 1 0 0 VREG1OUT x 0.96
0 1 1 0 1 VREG1OUT x 0.99
0 1 1 1 0 VREG1OUT x 1.02
0
1
1
1
1
Setting disabled
1 0 0 0 0 VREG1OUT x 1.05
1 0 0 0 1 VREG1OUT x 1.08
1 0 0 1 0 VREG1OUT x 1.11
1 0 0 1 1 VREG1OUT x 1.14
1 0 1 0 0 VREG1OUT x 1.17
1 0 1 0 1 VREG1OUT x 1.20
1 0 1 1 0 VREG1OUT x 1.23
1011
Setting disabled
11*
*
*
Setting disabled
Note 1) Adjust VREG1OUT and VCM0-4 to set VcomH the same level as VDH or less.
Note 2) Adjust VREG1OUT and VDV0-4 to set the amplitude of Vcom 0.6V or less.
RAM Address Set (R21h)
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5
AD AD AD AD AD AD AD AD AD AD AD
15 14 13 12 11 10 9 8 7 6 5
IB4 IB3 IB2
AD AD AD
4 32
IB1 IB0
AD AD
10
AD15–0: Make the initial setting of GRAM address in the address counter (AC). After GRAM data are
written, the address counter is automatically updated according to the settings with AM, I/D bits and the
setting for a new GRAM address is not required in the address counter. Therefore, data are written
consecutively without resetting the address. The address counter is not automatically updated when data
are read out from GRAM.
GRAM address setting can not be made during the standby mode. An address set should be made within
the area specified with the window address.
When the RGB interface is selected (RM = 1), the setting of the address for AD15-0 is made every frame at
the falling edge of VSYNC. When the internal clock operation or VSYNC interface is selected (RM = 0),
the setting of the address is made when the instruction is executed.
Rev.0.12, May 09 2003, page 53 of 156