HD66789 Datasheet, PDF (143/156 Pages) Renesas Technology Corp – 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit

HD66789
Preliminary
High-Speed Write Mode (HWM=1) (Vcc = 1.8 to 2.4 V)
Item
Symbol Unit Test Condition Min Typ Max
Bus cycle time Write
t_CYCW
ns
Figure 2
Read
t_CYCR
ns
Figure 2
Write low-level pulse width
PW_LW ns
Figure 2
Read low-level pulse width
PW_LR ns
Figure 2
Write high-level pulse width
PW_HW ns
Figure 2
Read high-level pulse width
PW_HR ns
Figure 2
Write/Read rise/fall time
t_{WRr, WRf} ns
Figure 2
Write (RS to CS*, WR*)
T.B.D. Set up time
Read (RS to CS*, RD*)
Address hold time
VLD setup time
t_AS
ns
t_AH
ns
t_VS
ns
Figure 2
Figure 2
Figure 2
VLD hold time
t_VH
ns
Figure 2
Write data set up time
t_DSW
ns
Figure 2
Write data hold time
t_H
ns
Figure 2
Read data delay time
t_DDR
ns
Figure 2
Read data hold time
t_DHR
ns
Figure 2
200 — —
800 — —
90 — —
350 — —
90 — —
400 — —
— — 25
0
——
10 — —
5
——
60 — —
15 — —
60 — —
15 — —
— — 200
5—
—
Normal Write Mode (HWM=0) : Vcc = 2.4 to 3.7 V
Item
Symbol Unit Test Condition Min Typ Max
Bus cycle time
Write
Read
t_CYCW
ns
t_CYCR
ns
Figure 2
Figure 2
250 —
—
500 —
—
Write low-level pulse width
PW_LW ns
Figure 2
40
—
—
Read low-level pulse width
PW_LR ns
Figure 2
250 —
—
Write high-level pulse width
PW_HW ns
Figure 2
70
—
—
T.B.D. ^{Read high-level pulse width}
PW_HR ns
Write/Read rise/fall time
t_{WRr, WRf} ns
Write (RS to CS*, WR*)
Set up time
t_AS
ns
Figure 2
Figure 2
Figure 2
200
—
0
—
—
—
—
25
—
Read (RS to CS*, WR*)
10
—
—
Address hold time
t_AH
ns
Figure 2
2
—
—
VLD set up time
t_VS
ns
Figure 2
25
—
—
VLD hold time
t_VH
ns
Figure 2
2
—
—
Write data setup time
t_DSW
ns
Figure 2
25
—
—
Write data hold time
t_H
ns
Figure 2
2
—
—
Read data delay time
t_DDR
ns
Figure 2
—
— 200
Read data hold time
t_DHR
ns
Figure 2
5
—
—
Rev.0.12, May 09 2003, page 143 of 156