|
4507_M Datasheet, PDF (88/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES | |||
|
◁ |
4507 Group
HARDWARE
INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
D9
D0
Number of
1001110000
270
2
16
words
1
Number of
cycles
1
Flag CY
â
Skip condition
â
Operation:
(B) â (T17âT14)
(A) â (T13âT10)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T17âT14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13âT10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
D9
D0
Number of
1001110001
271
2
16
words
1
Number of
cycles
1
Flag CY
â
Skip condition
â
Operation:
(B) â (T27âT24)
(A) â (T23âT20)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T27âT24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23âT20) of
timer 2 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
D9
D0
Number of
1001111001
279
2
16
words
1
Number of
cycles
1
Flag CY
â
Skip condition
â
Operation:
In A/D conversion mode (Q13 = 0),
(B) â (AD9âAD6)
(A) â (AD5âAD2)
In comparator mode (Q13 = 1),
(B) â (AD7âAD4)
(A) â (AD3âAD0)
(Q13 : bit 3 of A/D control register Q1)
Grouping:
Description:
A/D conversion operation
In the A/D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9âAD6) of register
AD to register B, and the middle-order 4 bits
(AD5âAD2) of register AD to register A. In the
comparator mode (Q13 = 1), transfers the high-
order 4 bits (AD7âAD4) of comparator register
to register B, and the low-order 4 bits (AD3â
AD0) of comparator register to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
D9
D0
Number of Number of Flag CY
0000101010
02A
words
cycles
2
16
1
1
â
Skip condition
â
Operation:
(B) â (E7âE4)
(A) â (E3âE0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7âE4) of
register E to register B, and low-order 4 bits
of register E to register A.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
1-76
|
▷ |