4507_M Datasheet, PDF (156/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.6 RAM back-up
2.6 RAM back-up
2.6.1 RAM back-up mode
The system enters RAM back-up mode when the POF2 instruction is executed after the EPOF instruction
is executed. Table 2.6.1 shows the function and state retained at RAM back-up mode. Also, Table 2.6.2
shows the return source from this state.
(1) RAM back-up mode
As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced
without losing the contents of RAM.
Table 2.6.1 Functions and states retained at RAM back-up mode
Function
RAM back-up
POF2
Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2)
✕
Contents of RAM
O
Port level
(Note 5)
Selected oscillation circuit
O
Timer control register W1
✕
Timer control registers W2, W6
O
Clock control register MR
✕
Interrupt control registers V1, V2
✕
Interrupt control register I1
O
Timer 1 function
✕
Timer 2 function
(Note 3)
A/D function
✕
Pull-up control registers PU0–PU2
O
Key-on wakeup control registers K0–K2
O
A/D control register Q1
O
External 0 interrupt request flag (EXF0)
✕
Timer 1 interrupt request flag (T1F)
✕
Timer 2 interrupt request flag (T2F)
(Note 3)
A/D conversion completion flag (ADF)
✕
Watchdog timer flags (WDF1, WDF2)
✕ (Note 4)
Watchdog timer enable flag (WEF)
✕
16-bit timer (WDT)
✕ (Note 4)
Interrupt enable flag (INTE)
✕
Notes 1: “O” represents that the function can be retained, and “✕” represents that the function is initialized.
Registers and flags other than the above are undefined at RAM back-up, and set an initial value
after returning.
2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then execute the POF2
instruction.
5: As for the D2/C pin, the output latch of port C is set to “1” at the RAM back-up. However, the
output latch of port D2 is retained.
As for the other ports, their output levels are retained at the RAM back-up.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-41