4507_M Datasheet, PDF (201/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPENDIX
3.3 List of precautions
3.3.4 Notes on interrupt
(1) Setting of INT interrupt valid waveform
Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of P13/INT pin, the external interrupt request flag (EXF0) may be set
to “1” when the interrupt valid waveform is changed.
(2) Setting of INT pin input control
Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction.
Depending on the input state of P13/INT pin, the external interrupt request flag (EXF0) may be set
to “1” when the interrupt valid waveform is changed.
(3) Multiple interrupts
Multiple interrupts cannot be used in the 4507 Group.
(4) Notes on interrupt processing
When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to “0” (interrupt
disable state). In order to enable the interrupt at the same time when system returns from the
interrupt, write EI and RTI instructions continuously.
(5) P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about
the following notes.
• Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may
be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 3.3.1 ➀) and then, change the bit 3
of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one
instruction (refer to Figure 3.3.1 ➁).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer
to Figure 3.3.1 ➂).
LA
TV1A
LA
TI1A
NOP
SNZ0
NOP
4 ; (✕✕✕02)
; The SNZ0 instruction is valid ..... ➀
8 ; (1✕✕✕2)
; Control of INT pin input is changed
; .......................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
; .......................................................... ➂
✕ : these bits are not used here.
Fig. 3.3.1 External 0 interrupt program example-1
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
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