4507_M Datasheet, PDF (35/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
HARDWARE
FUNCTION BLOCK OPERATIONS
(2) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 inter-
rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
Table 8 External interrupt control register
Interrupt control register I1
at reset : 00002
at RAM back-up : state retained
R/W
I13
INT pin input control bit (Note 2)
0
INT pin input disabled
1
INT pin input enabled
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
I11
INT pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT pin
I10
timer 1 control enable bit
0
Disabled
1
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-
struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
1-23