4507_M Datasheet, PDF (129/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.2 Interrupts
(4) A/D interrupt
The interrupt request occurs by the end of the A/D conversion.
s A/D interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the
interrupt enable flag INTE are set to “1.” When the A/D interrupt occurs, the interrupt processing
is executed from address C in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set
to “0.”
2.2.2 Related registers
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable.
Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE
flag is cleared to “0” with the DI instruction.
When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are
disabled until the EI instruction is executed.
Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more
instruction.
(2) Interrupt control register V1
Interrupt enable bit of external 0, timer 1 and timer 2 are assigned to register V1.
Set the contents of this register through register A with the TV1A instruction.
In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A.
Table 2.2.1 shows the interrupt control register V1.
Table 2.2.1 Interrupt control register V1
Interrupt control register V1
at reset : 00002
at RAM back-up : 00002
R/W
V13 Timer 2 interrupt enable bit
0 Interrupt disabled (SNZT2 instruction is valid)
1 Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
V12 Timer 1 interrupt enable bit
0 Interrupt disabled (SNZT1 instruction is valid)
1 Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
V11 Not used
0
This bit has no function, but read/write is enabled.
1
V10 External 0 interrupt enable bit
0 Interrupt disabled (SNZ0 instruction is valid)
1 Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When the interrupt is set, V11 is not used.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-14