4507_M Datasheet, PDF (47/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
HARDWARE
FUNCTION BLOCK OPERATIONS
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison volt-
ages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in
the low-order 4 bits of the comparator register with the TADAB in-
struction.
When changing from A/D conversion mode to comparator mode,
the result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from regis-
ter AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of com-
parison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref = ^VDD ✕ n
256
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input volt-
age with the comparison voltage. When the analog input voltage is
lower than the comparison voltage, the ADF flag is set to “1.” The
state of ADF flag can be examined with the skip instruction
(SNZAD). Use the interrupt control register V2 to select the inter-
rupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator oper-
ating.
The comparator stops 8 machine cycles after it has started (6 µs at
f(XIN) = 4.0 MHz in high-speed mode). When the analog input volt-
age is lower than the comparison voltage, the ADF flag is set to “1.”
(13) Notes for the use of A/D conversion 1
Note the following when using the analog input pins also for ports
P2 and P3 functions:
• Selection of analog input pins
Even when P20/AIN0, P21/AIN1, P30/AIN2, P31/AIN3 are set to pins
for analog input, they continue to function as ports P2 and P3 in-
put/output. Accordingly, when any of them are used as I/O port
and others are used as analog input pins, make sure to set the
outputs of pins that are set for analog input to “1.” Also, the port
input function of the pin functions as an analog input is unde-
fined.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of
register AD is transferred to the high-order 2 bits of register A, si-
multaneously, the low-order 2 bits of register A is “0.”
(14) Notes for the use of A/D conversion 2
Do not change the operating mode (both A/D conversion mode and
comparator mode) of A/D converter with the bit 3 of register Q1
while the A/D converter is operating.
When the operating mode of A/D converter is changed from the
comparator mode to A/D conversion mode with the bit 3 of register
Q1, note the following;
• Clear the bit 2 of register V2 to “0” to change the operating mode
of the A/D converter from the comparator mode to A/D conver-
sion mode with the bit 3 of register Q1.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the com-
parator mode to the A/D conversion mode. Accordingly, set a
value to the bit 3 of register Q1, and execute the SNZAD instruc-
tion to clear the ADF flag.
ADST instruction
Comparison result
store flag(ADF)
DAC operation signal
Fig. 31 Comparator operation timing chart
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
8 machine cycles
Comparator operation completed.
(The value of ADF is determined)
1-35