4507_M Datasheet, PDF (130/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.2 Interrupts
(3) Interrupt control register V2
Interrupt enable bit of A/D is assigned to register V2.
Set the contents of this register through register A with the TV2A instruction.
In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 2.2.2 shows the interrupt control register V2.
Table 2.2.2 Interrupt control register V2
Interrupt control register V2
at reset : 00002
at RAM back-up : 00002
R/W
V23 Not used
0
This bit has no function, but read/write is enabled.
1
V22 A/D interrupt enable bit
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid) (Note 2)
V21 Not used
0
This bit has no function, but read/write is enabled.
1
V20 Not used
0
This bit has no function, but read/write is enabled.
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This instruction is equivalent to the NOP instruction.
3: When the interrupt is set, V23, V21 and V20 are not used.
(4) Interrupt request flag
The activated condition for each interrupt is examined. Each interrupt request flag is set to “1” when
the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt
enable bit.
Each interrupt request flag is cleared to “0” when either;
•an interrupt occurs, or
•the next instruction is skipped with a skip instruction.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-15