4507_M Datasheet, PDF (128/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.2 Interrupts
2.2 Interrupts
The 4507 Group has four interrupt sources : external (INT), timer 1, timer 2, and A/D.
This section describes individual types of interrupts, related registers, application examples using interrupts
and notes.
2.2.1 Interrupt functions
(1) External 0 interrupt (INT)
The interrupt request occurs by the change of input level of INT pin.
The interrupt valid waveform can be selected by the bits 1 and 2, and the INT pin input is controlled
by the bit 3 of the interrupt control register I1.
s External 0 interrupt INT processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the external 0 interrupt occurs, the interrupt
processing is executed from address 0 in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set
to “0.”
(2) Timer 1 interrupt
The interrupt request occurs by the timer 1 underflow.
s Timer 1 interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 1 interrupt occurs, the interrupt processing
is executed from address 4 in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set
to “0.”
(3) Timer 2 interrupt
The interrupt request occurs by the timer 2 underflow.
s Timer 2 interrupt processing
q When the interrupt is used
The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the
interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing
is executed from address 6 in page 1.
q When the interrupt is not used
The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set
to “0.”
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-13