4507_M Datasheet, PDF (146/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.3 Timers
Continued from Figure 2.3.6 on the preceding page.
➇ Set Valid Waveform
Valid waveform of INT pin is selected.
INT pin input enabled, rising selected, Timer 1 control is enabled.
b3
b0
Interrupt control register I1 1 1 0 1 Rising edge detected (TI1A instruction)
➈ Set Auto-stop circuit
Timer 1 count auto-stop is selected.
b3
b0
Interrupt control register W2 _✕ 1 _{✕ ✕}
Timer 1 count auto-stop selected
(TW2A instruction)
➉ Clear Interrupt Request
INT interrupt activated condition is cleared.
External 0 interrupt request flag EXF0 “0”
INT interrupt activated condition cleared
(SNZ0 instruction)
Note when the interrupt request is cleared
When ➉ is executed, considering the skip of the next instruction according to the
interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
11 _{Enable Interrupts}
The timer 1 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
✕ 1✕✕
Timer 1 interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
“✕”: it can be “0” or “1.”
Timer start by external input
Fig. 2.3.7 Timer start by external input setting example (2)
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-31