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4507_M Datasheet, PDF (133/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES | |||
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4507 Group
APPLICATION
2.2 Interrupts
â Disable Interrupts
INT interrupt is temporarily disabled.
Interrupt enable flag INTE â0â
All interrupts disabled (DI instruction)
b3
b0 INT interrupt occurrence disabled
Interrupt control register V1 â â â 0 (TV1A instruction)
â Set Port
Port used for INT interrupt is set to input port.
b3
b0
Port P13 output latch 1 â â â Set to input (OP1A instruction)
â Set Valid Waveform
Valid waveform of INT pin is selected.
Both edges detection selected
b3
b0
Interrupt control register I1 1 â 1 â Both edges detection selected (TI1A instruction)
â Execute NOP Instruction
NOP instruction
â Clear Interrupt Request
INT interrupt activated condition is cleared.
INT interrupt request flag EXF0 â0â
INT interrupt activated condition cleared
(SNZ0 instruction)
Note when the interrupt request is cleared
When â is executed, considering the skip of the next instruction according to the
interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
â
Enable Interrupts
The INT interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
â
ââ
b0
1
INT interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE â1â
All interrupts enabled (EI instruction)
âââ: it can be â0â or â1.â
INT interrupt execution started
Fig. 2.2.2 INT interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-18
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