4507_M Datasheet, PDF (8/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
List of figures
List of figures
CHAPTER 1 HARDWARE
Pin configuration (top view) (4507 Group) ................................................................................. 1-2
Block diagram (4507 Group) ........................................................................................................ 1-3
Port block diagram (1) ................................................................................................................... 1-8
Port block diagram (2) ................................................................................................................... 1-9
Port block diagram (3) ................................................................................................................. 1-10
Port block diagram (4) ................................................................................................................. 1-11
External interrupt circuit structure .............................................................................................. 1-12
Fig. 1 AMC instruction execution example ............................................................................... 1-13
Fig. 2 RAR instruction execution example ............................................................................... 1-13
Fig. 3 Registers A, B and register E ........................................................................................ 1-13
Fig. 4 TABP p instruction execution example .......................................................................... 1-13
Fig. 5 Stack registers (SKs) structure ....................................................................................... 1-14
Fig. 6 Example of operation at subroutine call ....................................................................... 1-14
Fig. 7 Program counter (PC) structure ..................................................................................... 1-15
Fig. 8 Data pointer (DP) structure ............................................................................................. 1-15
Fig. 9 SD instruction execution example .................................................................................. 1-15
Fig. 10 ROM map of M34507M4/M34507E4 ............................................................................ 1-16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure ......................................................... 1-16
Fig. 12 RAM map ......................................................................................................................... 1-17
Fig. 13 Program example of interrupt processing ................................................................... 1-19
Fig. 14 Internal state when interrupt occurs ............................................................................ 1-19
Fig. 15 Interrupt system diagram ............................................................................................... 1-19
Fig. 16 Interrupt sequence .......................................................................................................... 1-21
Fig. 17 External interrupt circuit structure ................................................................................ 1-22
Fig. 18 External 0 interrupt program example-1 ...................................................................... 1-24
Fig. 19 External 0 interrupt program example-2 ...................................................................... 1-24
Fig. 20 External 0 interrupt program example-3 ...................................................................... 1-24
Fig. 21 Auto-reload function ....................................................................................................... 1-25
Fig. 22 Timers structure .............................................................................................................. 1-26
Fig. 23 Count timing diagram at CNTR input .......................................................................... 1-29
Fig. 24 Timer count start timing and count time when operation starts (T1, T2) ............... 1-29
Fig. 25 Watchdog timer function ................................................................................................ 1-30
Fig. 26 Program example to start/stop watchdog timer ......................................................... 1-31
Fig. 27 Program example to enter the RAM back-up mode when using the watchdog timer .. 1-31
Fig. 28 A/D conversion circuit structure ................................................................................... 1-32
Fig. 29 A/D conversion timing chart .......................................................................................... 1-34
Fig. 30 Setting registers .............................................................................................................. 1-34
Fig. 31 Comparator operation timing chart ............................................................................... 1-35
Fig. 32 Definition of A/D conversion accuracy ........................................................................ 1-36
Fig. 33 Reset release timing ...................................................................................................... 1-37
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Fig. 34 RESET pin input waveform and reset operation ....................................................... 1-37
Fig. 35 Structure of reset pin and its peripherals, and power-on reset operation ............. 1-38
Fig. 36 Internal state at reset .................................................................................................... 1-39
Fig. 37 State transition ................................................................................................................ 1-42
Fig. 38 Set source and clear source of the P flag ................................................................. 1-42
Fig. 39 Start condition identified example using the SNZP instruction ................................ 1-42
Fig. 40 Clock control circuit structure ....................................................................................... 1-45
Fig. 41 Switch to ceramic resonance/RC oscillation ............................................................... 1-46
Rev.2.01 Feb 04, 2005
iv
REJ09B0195-0201