4507_M Datasheet, PDF (117/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.1 I/O pins
2.1 I/O pins
The 4507 Group has the eighteen I/O pins. (Port P12 is also used as CNTR I/O pin, Port P13 is also used
as INT input pin, Port P2 is also used as analog input pins AIN0 and AIN1, Port P3 is also used as analog
input pins AIN2 and AIN3, Port D2 is also used as Port C, and Port D3 is also used as Port K, respectively).
This section describes each port I/O function, related registers, application example using each port function
and notes.
2.1.1 I/O ports
(1) Port P0
Port P0 is a 4-bit I/O port.
Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor
which turns ON/OFF with register PU0.
s Input/output of port P0
q Data input to port P0
Set the output latch of specified port P0i (i=0 to 3) to “1” with the OP0A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P0 is transferred to register A when the IAP0 instruction is executed.
q Data output from port P0
The contents of register A is output to port P0 with the OP0A instruction.
The output structure is an N-channel open-drain.
(2) Port P1
Port P1 is a 4-bit I/O port.
Port P1 has the key-on wakeup function which turns ON/OFF with register K1 and pull-up transistor
which turns ON/OFF with register PU1.
s Input/output of port P1
q Data input to port P1
Set the output latch of specified port P1i (i=0 to 3) to “1” with the OP1A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P1 is transferred to register A when the IAP1 instruction is executed.
q Data output from port P1
The contents of register A is output to port P1 with the OP1A instruction.
The output structure is an N-channel open-drain.
Note: Port P12 is also used as CNTR. Accordingly, when it is used as port P12, set “0” to the
timer control register W60.
Rev.2.01 Feb 04, 2005
2-2
REJ09B0195-0201