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4507_M Datasheet, PDF (36/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES | |||
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4507 Group
HARDWARE
FUNCTION BLOCK OPERATIONS
(3) Notes on interrupts
â Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
â Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
⢠Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 18â)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 18â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 18â).
⢠Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 20â)
and then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 20â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 20â).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Control of INT pin input is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (â1ââ2)
; Interrupt valid waveform is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
â : these bits are not used here.
Fig. 20 External 0 interrupt program example-3
â Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to â0â, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
⢠When the key-on wakeup function of port P13 is not used (regis-
ter K13 = â0â), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 19â).
LA 0
TI1A
DI
EPOF
POF
; (00ââ2)
; Input of INT disabled ........................ â
; RAM back-up
â : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
1-24
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