4507_M Datasheet, PDF (165/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
APPLICATION
2.7 Oscillation circuit
2.7.2 Oscillation operation
System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer
operation. For the 4507 Group, the clock supplied from the on-chip oscillator (internal oscillator) or the
ceramic resonance circuit, RC oscillation circuit is selected from the high-speed mode (f(XIN)), middle-
speed mode (f(XIN)/2), low-speed mode (f(XIN)/4) or default mode (f(XIN)/8) with the register MR.
Figure 2.7.5 shows the structure of the clock control circuit.
On-chip oscillator
(internal oscillator)
(Note 1)
RC oscillation circuit
XIN
XOUT
Ceramic resonator
circuit
Multiplexer
Division circuit
divided by 8
divided by 4
divided by 2
QS
QR
MR3, MR2
11
10
01
00
QS
R
System clock
Internal clock
generation circuit
(divided by 3)
Instruction clock
Counter
Wait time (Note 2) Program
control circuit
start signal
CRCK instruction
QS
R
QS
R
CMCK
instruction
RESET pin
Key-on wakeup signal
EPOF instruction + (POF2instruction)
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction
is executed after system is released from reset.
2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
After the certain oscillation stabilizing wait time elapses, the program start signal is output.
This circuit operates when system is released from reset or returned from RAM back-up.
Fig. 2.7.5 Structure of clock control circuit
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
2-50