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4507_M Datasheet, PDF (202/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES | |||
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4507 Group
APPENDIX
3.3 List of precautions
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to â0â, the RAM back-up mode is selected and the input of
INT pin is disabled, be careful about the following notes.
⢠When the key-on wakeup function of port P13 is not used (register K13 = â0â), clear bits 2 and 3
of register I1 before system enters to the RAM back-up mode. (refer to Figure 3.3.2 â).
LA
TI1A
DI
EPOF
POF2
0 ; (00ââ2)
; Input of INT disabled .................... â
; RAM back-up
â : these bits are not used here.
Fig. 3.3.2 External 0 interrupt program example-2
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in
software, be careful about the following notes.
⢠Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may
be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 3.3.3 â) and then, change the bit 2
of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to â0â after executing at least one
instruction (refer to Figure 3.3.3 â).
Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer
to Figure 3.3.3 â).
LA 4 ; (âââ02)
TV1A ; The SNZ0 instruction is valid ..... â
LA 12 ; (â1ââ2)
TI1A
; Interrupt valid waveform is changed
NOP
........................................................... â
SNZ0 ; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
........................................................... â
â : these bits are not used here.
Fig. 3.3.3 External 0 interrupt program example-3
(6) Power down instruction
Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
3-36
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