4507_M Datasheet, PDF (63/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
Interrupt control register V2
V23
Not used
V22
A/D interrupt enable bit
V21
Not used
V20
Not used
at reset : 00002
at RAM back-up : 00002
R/W
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
at reset : 00002
at RAM back-up : 00002
R/W
0
1
This bit has no function, but read/write is enabled.
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid) (Note 2)
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
Interrupt control register I1
I13
INT pin input control bit (Note 3)
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 3)
I11
INT pin edge detection circuit control bit
INT pin
I10
timer 1 control enable bit
at reset : 00002
at RAM back-up : state retained
R/W
0
INT pin input disabled
1
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
Clock control register MR
at reset : 11002
at RAM back-up : 11002
R/W
MR3
MR2
System clock selection bits
MR1 Not used
MR0 Not used
MR3 MR2
System clock
0 0 f(XIN) (high-speed mode)
0 1 f(XIN)/2 (middle-speed mode)
1 0 f(XIN)/4 (low-speed mode)
1 1 _{f(XIN)/8 (default mode)}
0
1
This bit has no function, but read/write is enabled.
0
1
This bit has no function, but read/write is enabled.
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-
struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
1-51