4507_M Datasheet, PDF (56/216 Pages) Renesas Technology Corp – 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES

4507 Group
HARDWARE
FUNCTION BLOCK OPERATIONS
Table 18 Pull-up control register and interrupt control register
PU03
PU02
PU01
PU00
Pull-up control register PU0
Port P03 pull-up transistor
control bit
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
at reset : 00002
at RAM back-up : state retained
W
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
PU13
PU12
PU11
PU10
Pull-up control register PU1
Port P13/INT pull-up transistor
control bit
Port P12/CNTR pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
at reset : 00002
at RAM back-up : state retained
W
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
PU23
PU22
PU21
PU20
Pull-up control register PU2
Port D3/K pull-up transistor
control bit
Port D2/C pull-up transistor
control bit
Port P21/AIN1 pull-up transistor
control bit
Port P20/AIN0 pull-up transistor
control bit
at reset : 00002
at RAM back-up : state retained
W
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
Interrupt control register I1
at reset : 00002
at RAM back-up : state retained
R/W
I13
INT pin input control bit (Note 2)
0
INT pin input disabled
1
INT pin input enabled
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
I11
INT pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT pin
I10
timer 1 control enable bit
0
Disabled
1
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-
struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
Rev.2.01 Feb 04, 2005
REJ09B0195-0201
1-44