SAA7104E Datasheet, PDF (9/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
handbook, halfpage
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MHC566
SAA7104E
SAA7105E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig.2 Pin configuration.
7 FUNCTIONAL DESCRIPTION
The digital video encoder encodes digital luminance and
colour difference signals (C_B-Y-C_R) or digital RGB signals
into analog CVBS, S-video and, optionally, RGB or
C_R-Y-C_B signals. NTSC M, PAL B/G and sub-standards
are supported.
The SAA7104E; SAA7105E can be directly connected to a
PC video graphics controller with a maximum resolution of
1280 × 1024 (progressive) or 1920 × 1080 (interlaced) at
a 50 or 60 Hz frame rate. A programmable scaler scales
the computer graphics picture so that it will fit into a
standard TV screen with an adjustable underscan area.
Non-interlaced-to-interlaced conversion is optimized with
an adjustable anti-flicker filter for a flicker-free display at a
very high sharpness.
Besides the most common 16-bit 4 : 2 : 2 C_B-Y-C_R input
format (using 8 pins with double edge clocking), other
C_B-Y-C_R and RGB formats are also supported; see
Tables 9 to 14.
A complete 3 × 256 bytes Look-Up Table (LUT), which can
be used, for example, as a separate gamma corrector, is
located in the RGB domain; it can be loaded either through
the video input port PD (Pixel Data) or via the I²C-bus.
The SAA7104E; SAA7105E supports a 32 × 32 × 2-bit
hardware cursor, the pattern of which can also be loaded
through the video input port or via the I²C-bus.
It is also possible to encode interlaced 4 : 2 : 2 video
signals such as PC-DVD; for that the anti-flicker filter, and
in most cases the scaler, will simply be bypassed.
Besides the applications for video output, the SAA7104E;
SAA7105E can also be used for generating a kind of
auxiliary VGA output, when the RGB non-interlaced input
signal is fed to the DACs. This may be of interest for
example, when the graphics controller provides a second
graphics window at its video output port.
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals at a crystal-stable clock rate of
13.5 MHz (independent of the actual pixel clock used at
the input side), corresponding to an internal 4 : 2 : 2
bandwidth in the luminance/colour difference domain.
Luminance and chrominance signals are filtered in
accordance with the standard requirements of “RS-170-A”
and “ITU-R BT.470-3”.
For ease of analog post filtering the signals are twice
oversampled to 27 MHz before digital-to-analog
conversion.
The total filter transfer characteristics (scaler and
anti-flicker filter are not taken into account) are illustrated
in Figs 4 to 9. All three DACs are realized with full 10-bit
resolution. The C_R-Y-C_B to RGB dematrix can be
bypassed (optionally) in order to provide the upsampled
C_R-Y-C_B input signals.
2004 Mar 04
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