SAA7104E Datasheet, PDF (28/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
7.23 I²C-bus format
Table 17 I²C-bus write access to control registers; see Table 23
S
10001000
A
SUBADDRESS
A DATA 0 A --------
DATA n A P
Table 18 I²C-bus write access to the HD line count array (subaddress D0H); see Table 23
S 1 0 0 0 1 0 0 0 A D0H A RAM ADDRESS A DATA 00 A DATA 01 A -------- DATA n A P
Table 19 I²C-bus write access to cursor bit map (subaddress FEH); see Table 23
S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A DATA 0 A --------
DATA n A P
Table 20 I²C-bus write access to colour look-up table (subaddress FFH); see Table 23
S 1 0 0 0 1 0 0 0 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A -------- P
Table 21 I²C-bus read access to control registers; see Table 23
S 1 0 0 0 1 0 0 0 A SUBADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P
Table 22 I²C-bus read access to cursor bit map or colour LUT; see Table 23
S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P
or
FFH
Table 23 Explanations of Tables 17 to 22
CODE
S
Sr
1 0 0 0 1 0 0 X; note 1
A
Am
SUBADDRESS; note 2
DATA
--------
P
RAM ADDRESS
DESCRIPTION
START condition
repeated START condition
slave address
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte
data byte
continued data bytes and acknowledges
STOP condition
start address for RAM access
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.
2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
2004 Mar 04
28