SAA7104E Datasheet, PDF (14/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode Closed Caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.
7.12.5 ANTI-TAPING (SAA7104E ONLY)
For more information contact your nearest Philips
Semiconductors sales office.
7.13 RGB processor
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, C_B and C_R signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 8 and 9.
7.14 Triple DAC
Both Y and C signals are converted from digital-to-analog
in a 10-bit resolution at the output of the video encoder.
Y and C signals are also combined into a 10-bit CVBS
signal.
The CVBS output signal occurs with the same processing
delay as the Y, C and optional RGB or C_R-Y-C_B outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by ¹⁵⁄₁₆ with respect to Y and C DACs to make
maximum use of the conversion ranges.
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 10-bit resolution.
The reference currents of all three DACs can be adjusted
individually in order to adapt for different output signals.
In addition, all reference currents can be adjusted
commonly to compensate for small tolerances of the
on-chip band gap reference voltage.
Alternatively, all currents can be switched off to reduce
power dissipation.
All three outputs can be used to sense for an external load
(usually 75 Ω) during a pre-defined output. A flag in the
I²C-bus status byte reflects whether a load is applied or
not. In addition, an automatic sense mode can be
activated which indicates a 75 Ω load at any of the three
outputs at the dedicated interrupt pin TVD.
If the SAA7104E; SAA7105E is required to drive a second
(auxiliary) VGA monitor or an HDTV set, the DACs receive
the signal coming from the HD data path. In this event, the
DACs are clocked at the incoming PIXCLKI instead of the
27 MHz crystal clock used in the video encoder.
7.15 HD data path
This data path allows the SAA7104E; SAA7105E to be
used with VGA or HDTV monitors. It receives its data
directly from the cursor generator and supports RGB and
Y-P_B-P_R output formats (RGB not with Y-P_B-P_R input
formats). No scaling is done in this mode.
A gain adjustment either leads the full level swing to the
digital-to-analog converters or reduces the amplitude by a
factor of 0.69. This enables sync pulses to be added to the
signal as it is required for display units expecting signals
with sync pulses, either regular or 3-level syncs.
7.16 Timing generator
The synchronization of the SAA7104E; SAA7105E is able
to operate in two modes; slave mode and master mode.
In slave mode, the circuit accepts sync pulses on the
bidirectional FSVGC (frame sync), VSVGC (vertical sync)
and HSVGC (horizontal sync) pins: the polarities of the
signals can be programmed. The frame sync signal is only
necessary when the input signal is interlaced, in other
cases it may be omitted. If the frame sync signal is present,
it is possible to derive the vertical and the horizontal phase
from it by setting the HFS and VFS bits. HSVGC and
VSVGC are not necessary in this case, so it is possible to
switch the pins to output mode.
Alternatively, the device can be triggered by auxiliary
codes in a ITU-R BT.656 data stream via PD7 to PD0.
Only vertical frequencies of 50 and 60 Hz are allowed with
the SAA7104E; SAA7105E. In slave mode, it is not
possible to lock the encoders colour carrier to the line
frequency with the PHRES bits.
In the (more common) master mode, the time base of the
circuit is continuously free-running. The IC can output a
frame sync at pin FSVGC, a vertical sync at pin VSVGC, a
horizontal sync at pin HSVGC and a composite blanking
signal at pin CBO. All of these signals are defined in the
PIXCLK domain. The duration of HSVGC and VSVGC are
fixed, they are 64 clocks for HSVGC and 1 line for VSVGC.
The leading slopes are in phase and the polarities can be
programmed.
2004 Mar 04
14