SAA7104E Datasheet, PDF (37/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 49 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
FSC0 to FSC3 f_fsc = subcarrier frequency (in multiples
of line frequency); f_llc = clock frequency
(in multiples of line frequency)
CONDITIONS
REMARKS
FSC
=
round


f-f-_f-l-s-l-c-c
×
2³²_
;
FSC3 = most significant byte;
FSC0 = least significant byte
note 1
Note
1. Examples:
a) NTSC M: f_fsc = 227.5, f_llc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL B/G: f_fsc = 283.7516, f_llc = 1728 → FSC = 705268427 (2A098ACBH).
Table 50 Subaddresses 67H to 6AH
DATA BYTE
L21O0
L21O1
L21E0
L21E1
DESCRIPTION
REMARKS
first byte of captioning data, odd field LSBs of the respective bytes are encoded immediately
second byte of captioning data, odd field ^{after run-in and framing code, the MSBs of the respective}
first byte of extended data, even field
bytes have to carry the parity bit, in accordance with the
definition of line 21 encoding format.
second byte of extended data, even field
Table 51 Subaddresses 6CH and 6DH
DATA BYTE
HTRIG
DESCRIPTION
sets the horizontal trigger phase related to chip-internal horizontal input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; the default value is 0
Table 52 Subaddress 6DH
DATA BYTE
VTRIG
DESCRIPTION
sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
Table 53 Subaddress 6EH
DATA BYTE
NVTRIG
BLCKON
PHRES
LDEL
FLC
LOGIC
LEVEL
DESCRIPTION
0 values of the VTRIG register are positive
1 values of the VTRIG register are negative
0 encoder in normal operation mode; default after reset
1 output signal is forced to blanking level
− selects the phase reset mode of the colour subcarrier generator; see Table 54
− selects the delay on luminance path with reference to chrominance path; see Table 55
− field length control; see Table 56
2004 Mar 04
37