SAA7104E Datasheet, PDF (20/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
7.20.4 VERTICAL SCALER
The input vertical offset can be taken from the assumption
that the scaler should just have finished writing the first line
when the encoder starts reading it:
YOFS = ^{F----A----L-I--n--×}-P----1p----l7--_×-1---6-T----P^×----c-T--l-k-X----c---l-k-- – 2.5 (60 Hz)
YOFS = ^{F----A----L-I--n--×}-P----1p----l7--_×-2---8-T----P^×----c-T--l-k-X----c---l-k-- – 2.5 (50 Hz)
In most cases the vertical offsets will be the same for odd
and even fields. The results should be rounded down.
YPIX = InLin
YSKIP defines the anti-flicker function. 0 means maximum
flicker reduction but minimum vertical bandwidth, 4095
gives no flicker reduction and maximum bandwidth. Note
that the maximum value for YINC is 4095. It might be
necessary to reduce the value of YSKIP to fulfil this
requirement.
YINC = _{I--n-O---L--u-i-n-t--L--+}-i-n---2-- × _1 + ^{Y--4---S-0---K-9---I5-P---}_ × 4096
YIWGTO = ^{Y-----I-2N-----C--} + 2048
YIWGTE = ^{Y-----I-N-----C-----–}--2---Y----S----K----I--P--
When YINC = 0 it sets the scaler to scaling factor 1. The
initial weighting factors must not be set to 0 in this case.
YIWGTE may go negative. In this event, YINC should be
added and YOFSE incremented. This can be repeated as
often as necessary to make YIWGTE positive.
It should be noted that these equations assume that the
input is non-interlaced but the output is interlaced. If the
input is interlaced, the initial weighting factors need to be
adapted to obtain the proper phase offsets in the output
frame.
If vertical upscaling beyond the upper capabilities is
required, the parameter YUPSC may be set to logic 1. This
extends the maximum vertical scaling factor by a factor
of 2. Only the parameter YINC is affected, it needs to be
divided by two to get the same effect.
There are restrictions in this mode:
• The vertical filter YFILT is not available in this mode; the
circuit will ignore this value
• The horizontal blanking needs to be long enough to
transfer an output line between 2 memory locations.
This is 710 internal pixel clocks.
Or the upscaling factor needs to be limited to 1.5 and the
horizontal upscaling factor is also limited to less than
∼1.5. In this case a normal blanking length is sufficient.
7.21 Input levels and formats
The SAA7104E; SAA7105E accepts digital Y, C_B, C_R or
RGB data with levels (digital codes) in accordance with
“ITU-R BT.601”. An optional gain adjustment also allows
to accept data with the full level swing of 0 to 255.
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated for by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
The RGB, respectively C_R-Y-C_B path features an
individual gain setting for luminance (GY) and colour
difference signals (GCD). Reference levels are measured
with a colour bar, 100% white, 100% amplitude and
100% saturation.
The SAA7104E; SAA7105E has special input cells for the
VGC port. They operate at a wider supply voltage range
and have a strict input threshold at ¹/₂V_DDD. To achieve full
speed of these cells, the EIDIV bit needs to be set to
logic 1. Note that the impedance of these cells is
approximately 6 kΩ. This may cause trouble with the
bootstrapping pins of some graphic chips. So the
power-on reset forces the bit to logic 0, the input
impedance is regular in this mode.
Table 7 “ITU-R BT.601” signal component levels
COLOUR
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
SIGNALS⁽¹⁾
Y C_B C_R R
G
B
235 128 128 235 235 235
210 16 146 235 235 16
170 166 16 16 235 235
145 54 34 16 235 16
106 202 222 235 16 235
81 90 240 235 16 16
41 240 110 16 16 235
16 128 128 16 16 16
Note
1. Transformation:
a) R = Y + 1.3707 × (C_R − 128)
b) G = Y − 0.3365 × (C_B − 128) − 0.6982 × (C_R − 128)
c) B = Y + 1.7324 × (C_B − 128).
2004 Mar 04
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