SAA7104E Datasheet, PDF (30/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 28 Subaddress 1BH
DATA BYTE
MSM
MSA
MSOE
RCOMP
(read only)
GCOMP
(read only)
BCOMP
(read only)
LOGIC
LEVEL
DESCRIPTION
0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset
1 monitor sense mode on
0 automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default
after reset
1 automatic monitor sense mode on if MSM = 0
0 pin TVD is active
1 pin TVD is 3-state; default after reset
0 check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded
1 check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded
0 check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded
1 check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded
0 check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded
1 check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
Table 29 Subaddresses 26H and 27H
DATA BYTE
WSS
WSSON
LOGIC
LEVEL
DESCRIPTION
− wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
0 wide screen signalling output is disabled; default after reset
1 wide screen signalling output is enabled
Table 30 Subaddress 28H
DATA BYTE
BS
LOGIC
LEVEL
DESCRIPTION
− starting point of burst in clock cycles
REMARKS
PAL: BS = 33 (21H); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BS = 25 (19H); default after reset if
strapping pin FSVGC tied to LOW
2004 Mar 04
30