SAA7104E Datasheet, PDF (38/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 54 Logic levels and function of PHRES
DATA BYTE
PHRES1
0
0
1
1
PHRES0
0
1
0
1
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
DESCRIPTION
Table 55 Logic levels and function of LDEL
DATA BYTE
LDEL1
0
0
1
1
LDEL0
0
1
0
1
DESCRIPTION
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
Table 56 Logic levels and function of FLC
DATA BYTE
FLC1
0
0
1
1
FLC0
0
1
0
1
DESCRIPTION
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 57 Subaddress 6FH
DATA
BYTE
CCEN
TTXEN
SCCLN
LOGIC
LEVEL
−
0
1
−
DESCRIPTION
enables individual line 21 encoding; see Table 58
disables teletext insertion; default after reset
enables teletext insertion
selects the actual line, where Closed Caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 58 Logic levels and function of CCEN
DATA BYTE
CCEN1
0
0
1
1
CCEN0
0
1
0
1
DESCRIPTION
line 21 encoding off; default after reset
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
2004 Mar 04
38