SAA7104E Datasheet, PDF (12/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
7.5 RGB Y-C_B-C_R matrix
RGB input signals to be encoded to PAL or NTSC are
converted to the Y-C_B-C_R colour space in this block. The
colour difference signals are fed through low-pass filters
and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream
for further processing.
A gain adjust option corrects the level swing of the
graphics world (black-to-white as 0 to 255) to the required
range of 16 to 235.
The matrix and formatting blocks can be bypassed for
Y-C_B-C_R graphics input.
When the auxiliary VGA mode is selected, the output of the
cursor insertion block is immediately directed to the triple
DAC.
7.6 Horizontal scaler
The high quality horizontal scaler operates on the 4 : 2 : 2
data stream. Its control engines compensate the colour
phase offset automatically.
The scaler starts processing after a programmable
horizontal offset and continues with a number of input
pixels. Each input pixel is a programmable fraction of the
current output pixel (XINC/4096). A special case is
XINC = 0, this sets the scaling factor to 1.
If the SAA7104E; SAA7105E input data is in accordance
with “ITU-R BT.656”, the scaler enters another mode.
In this event, XINC needs to be set to 2048 for a scaling
factor of 1. With higher values, upscaling will occur.
The phase resolution of the circuit is 12 bits, giving a
maximum offset of 0.2 after 800 input pixels. Small FIFOs
rearrange a 4 : 2 : 2 data stream at the scaler output.
7.7 Vertical scaler and anti-flicker filter
The functions scaling, Anti-Flicker Filter (AFF) and
re-interlacing are implemented in the vertical scaler.
Besides the entire input frame, it receives the first and last
lines of the border to allow anti-flicker filtering.
The circuit generates the interlaced output fields by scaling
down the input frames with different offsets for odd and
even fields. Increasing the YSKIP setting reduces the
anti-flicker function. A YSKIP value of 4095 switches it off;
see Table 86.
An additional, programmable vertical filter supports the
anti-flicker function. This filter is not available at upscaling
factors of more than 2.
The programming is similar to the horizontal scaler. For the
re-interlacing, the resolutions of the offset registers are not
sufficient, so the weighting factors for the first lines can
also be adjusted. YINC = 0 sets the scaling factor to 1;
YIWGTO and YIWGTE must not be 0.
Due to the re-interlacing, the circuit can perform upscaling
by a maximum factor of 2. The maximum factor depends
on the setting of the anti-flicker function and can be derived
from the formulae given in Section 7.20.
An additional upscaling mode allows to increase the
upscaling factor to maximum 4 as it is required for the old
VGA modes like 320 × 240.
7.8 FIFO
The FIFO acts as a buffer to translate from the PIXCLK
clock domain to the XTAL clock domain. The write clock is
PIXCLK and the read clock is XTAL. An underflow or
overflow condition can be detected via the I²C-bus read
access.
In order to avoid underflows and overflows, it is essential
that the frequency of the synthesized PIXCLK matches to
the input graphics resolution and the desired scaling
factor.
7.9 Border generator
When the graphics picture is to be displayed as interlaced
PAL, NTSC, S-video or RGB on a TV screen, it is desired
in many cases not to lose picture information due to the
inherent overscanning of a TV set. The desired amount of
underscan area, which is achieved through appropriate
scaling in the vertical and horizontal direction, can be filled
in the border generator with an arbitrary true colour tint.
7.10 Oscillator and Discrete Time Oscillator (DTO)
The master clock generation is realized as a 27 MHz
crystal oscillator, which can operate with either a
fundamental wave crystal or a 3rd-harmonic crystal.
The crystal clock supplies the DTO of the pixel clock
synthesizer, the video encoder and the I²C-bus control
block. It also usually supplies the triple DAC, with the
exception of the auxiliary VGA or HDTV mode, where the
triple DAC is clocked by the pixel clock (PIXCLK).
The DTO can be programmed to synthesize all relevant
pixel clock frequencies between circa 40 and 85 MHz.
Two programmable dividers provide the actual clock to be
used externally and internally. The dividers can be
programmed to factors of 1, 2, 4 and 8. For the internal
pixel clock, a divider ratio of 8 makes no sense and is thus
forbidden.
2004 Mar 04
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