SAA7104E Datasheet, PDF (40/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 64 Subaddresses 78H, 79H and 7CH
DATA BYTE
DESCRIPTION
TTXEVS
first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in even field
line = (TTXEVS + 4) for M-systems
line = (TTXEVS + 1) for other systems
TTXEVE
last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in even field
line = (TTXEVE + 3) for M-systems
line = TTXEVE for other systems
REMARKS
TTXEVS = 04H; is default
after reset if strapped to PAL
TTXEVS = 05H; is default
after reset if strapped to
NTSC
TTXEVE = 16H; is default
after reset if strapped to PAL
TTXEVE = 10H; is default
after reset if strapped to
NTSC
Table 65 Subaddresses 7AH to 7CH
DATA BYTE
DESCRIPTION
FAL
first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
last active line = LAL + 3 for M-systems and LAL for other system, measured in lines
LAL = 0 coincides with the first field synchronization pulse
Table 66 Subaddress 7CH
DATA BYTE
TTX60
TTXO
LOGIC
LEVEL
DESCRIPTION
0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset
1 enables world standard teletext 60 Hz (FISE = 1)
0 new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is
requested (see Fig.14); default after reset
1 old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH; the
length of the window depends on the chosen teletext standard (see Fig.14)
Table 67 Subaddresses 7EH and 7FH
DATA BYTE
DESCRIPTION
LINE
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)
this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
Table 68 Subaddresses 81H to 83H
DATA BYTE
DESCRIPTION
PCL
defines the frequency of the synthesized pixel clock PIXCLKO;
f_PIXCLK
=


P--2---C-_2--4-L--
×
f_{XTAL}
× 8 ; f_XTAL
=
27
MHz
nominal, e.g.
640 × 480 to NTSC M: PCL = 20F63BH;
640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
2004 Mar 04
40