SAA7104E Datasheet, PDF (42/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 74 Subaddresses 91H and 94H
DATA BYTE
DESCRIPTION
XPIX
pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
Table 75 Subaddresses 92H and 94H
DATA BYTE
DESCRIPTION
YOFSO
vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
Table 76 Subaddresses 93H and 94H
DATA BYTE
DESCRIPTION
YOFSE
vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 77 Subaddresses 95H and 96H
DATA BYTE
DESCRIPTION
YPIX
defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE − YOFSO
Table 78 Subaddress 96H
DATA BYTE
EFS
PCBN
SLAVE
ILC
YFIL
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
frame sync signal at pin FSVGC ignored in slave mode
frame sync signal at pin FSVGC accepted in slave mode
normal polarity of CBO signal (HIGH during active video)
inverted polarity of CBO signal (LOW during active video)
the SAA7104E; SAA7105E is timing master to the graphics controller
the SAA7104E; SAA7105E is timing slave to the graphics controller
if hardware cursor insertion is active, set LOW for non-interlaced input signals
if hardware cursor insertion is active, set HIGH for interlaced input signals
luminance sharpness booster disabled
luminance sharpness booster enabled
2004 Mar 04
42