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| SAA7104E Datasheet, PDF (21/70 Pages) NXP Semiconductors – Digital video encoder | |||
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Philips Semiconductors
Digital video encoder
Product speciï¬cation
SAA7104E; SAA7105E
Table 8 Usage of bits SLOT and EDGE
DATA SLOT CONTROL
(EXAMPLE FOR FORMAT 0)
SLOT EDGE
1st DATA
0
0 at rising edge
G3/Y3
0
1 at falling edge
G3/Y3
1
0 at rising edge
R7/CR7
1
1 at falling edge
R7/CR7
2nd DATA
at falling edge
R7/CR7
at rising edge
R7/CR7
at falling edge
G3/Y3
at rising edge
G3/Y3
Table 9 Pin assignment for input format 0
8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED
RGB/CB-Y-CR
PIN
FALLING
RISING
CLOCK EDGE CLOCK EDGE
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
G3/Y3
G2/Y2
G1/Y1
G0/Y0
B7/CB7
B6/CB6
B5/CB5
B4/CB4
B3/CB3
B2/CB2
B1/CB1
B0/CB0
R7/CR7
R6/CR6
R5/CR5
R4/CR4
R3/CR3
R2/CR2
R1/CR1
R0/CR0
G7/Y7
G6/Y6
G5/Y5
G4/Y4
Table 10 Pin assignment for input format 1
5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
PIN
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
FALLING
CLOCK EDGE
G2
G1
G0
B4
B3
B2
B1
B0
RISING
CLOCK EDGE
X
R4
R3
R2
R1
R0
G4
G3
Table 11 Pin assignment for input format 2
5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
PIN
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
FALLING
CLOCK EDGE
G2
G1
G0
B4
B3
B2
B1
B0
RISING
CLOCK EDGE
R4
R3
R2
R1
R0
G5
G4
G3
Table 12 Pin assignment for input format 3
8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR
FALLING RISING FALLING RISING
PIN
CLOCK CLOCK CLOCK CLOCK
EDGE EDGE EDGE EDGE
n
n
n+1
n+1
PD7
CB7(0) Y7(0) CR7(0) Y7(1)
PD6
CB6(0) Y6(0) CR6(0) Y6(1)
PD5
CB5(0) Y5(0) CR5(0) Y5(1)
PD4
CB4(0) Y4(0) CR4(0) Y4(1)
PD3
CB3(0) Y3(0) CR3(0) Y3(1)
PD2
CB2(0) Y2(0) CR2(0) Y2(1)
PD1
CB1(0) Y1(0) CR1(0) Y1(1)
PD0
CB0(0) Y0(0) CR0(0) Y0(1)
2004 Mar 04
21
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